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w wm8762 24-bit 192khz stereo dac wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, november 2011, rev 4.6 copyright ? 2011 wolfson microelectronics plc description the wm8762 is a high performance stereo dac designed for audio applications such as dvd, home theatre systems, and digital tv. the wm8762 supports data input word lengths from 16 to 24-bits and sampling rates up to 192khz. the wm8762 consists of a serial interface port, digital interpolation filters, multi-bit sigma delta modulators and stereo dac in a very small 8-pin soic package. the wm8762 supports a 16-24-bit left justified digital audio interface. the wm8762 is an ideal device to interface to ac-3 ? , dts ? , and mpeg audio decoders for surround sound applications, or for use in dvd players, including supporting the implementation of 2 channels at 192khz for high-end dvd-audio applications. features ? stereo dac ? audio performance - 98db snr (?a? weighted @ 48khz) - -84db thd ? sampling frequency: 8khz ? 192khz ? audio data interface format - 16-24-bit left justified ? 2.7v ? 5.5v supply operation ? 8-lead soic package applications ? dvd players ? digital tv ? digital set top box block diagram mute bckin voutl sigma delta modulator lrcin din mute sigma delta modulator digital filters mclk vdd gnd right dac left dac voutr w wm8762 serial interface
wm8762 production data w pd, rev 4.6, november 2011 2 table of contents description ............................................................................................................ 1 ? features ................................................................................................................. 1 ? applications .......................................................................................................... 1 ? block diagram ..................................................................................................... 1 ? table of contents .............................................................................................. 2 ? pin configuration ............................................................................................... 3 ? ordering information ....................................................................................... 3 ? pin description ..................................................................................................... 3 ? absolute maximum ratings ............................................................................. 4 ? dc electrical characteristics .................................................................... 5 ? electrical characteristics .......................................................................... 5 ? terminology ................................................................................................................... . 6 ? power on reset (por) ................................................................................................... 6 ? master clock timing ..................................................................................................... 8 ? digital audio interface ............................................................................................... 8 ? device description ............................................................................................. 9 ? general introduction ................................................................................................. 9 ? dac circuit description .............................................................................................. 9 ? clocking schemes ....................................................................................................... 10 ? digital audio interface ............................................................................................. 10 ? audio data sampling rates ...................................................................................... 10 ? digital filter characteristics .............................................................................. 11 ? dac filter responses ................................................................................................ 11 ? typical performance ...................................................................................... 12 ? applications information ............................................................................. 13 ? recommended external components ................................................................. 13 ? recommended external components values .................................................. 13 ? recommended analogue low pass filter (optional) .................................... 14 ? pcb layout recommendations ................................................................................ 14 ? package drawing .............................................................................................. 15 ? important notice .............................................................................................. 16 ? address: ...................................................................................................................... .... 16 ? revision history ................................................................................................ 17 ?
wm8762 production data w pd, rev 4.6, november 2011 3 pin configuration 8 7 6 5 wm8762 1 2 3 4 vdd voutl voutr gnd mclk lrcin din bckin ordering information device temperature range package moisture sensitivity level peak soldering temperature WM8762CGED -40 to +85 o c 8-lead soic (pb-free) msl1 260 o c WM8762CGED/r -40 to +85 o c 8-lead soic (pb-free, tape and reel) msl1 260 o c note: reel quantity = 3,000 pin description pin name type description 1 din digital input serial audio data input 2 bckin digital input bit clock input 3 lrcin digital input sample rate clock input 4 mclk digital input system master clock input 5 voutl analogue output left channel dac output 6 gnd supply analogue ground supply 7 vdd supply positive supply 8 voutr analogue output right channel dac output note: digital input pins have schmitt trigger input buffers.
wm8762 production data w pd, rev 4.6, november 2011 4 absolute maximum ratings absolute maximum ratings are stress ratings only. perm anent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guar anteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-st d-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltage -0.3v +7v voltage range digital inputs gnd -0.3v vdd +0.3v master clock frequency 50mhz operating temperature range, t a -40 ? c +85 ? c storage temperature after soldering -65 ? c +150 ? c
wm8762 production data w pd, rev 4.6, november 2011 5 dc electrical characteristics parameter symbol test conditions min typ max unit supply range vdd 2.7 5.5 v ground gnd 0 v supply current vdd = 5v 26 ma supply current vdd = 3.3v 20 ma power down current (note 3) vdd=3.3v 0.5 ma electrical characteristics test conditions vdd = 5v, gnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (ttl levels) input low level v il 0.8 v input high level v ih 2 v output low v ol i ol = 2ma 0.10 x vdd v output high v oh i oh = 2ma 0.9 x vdd v dac output (load = 10k ? 50pf) 0dbfs full scale output voltage at dac outputs 1.2 x vdd/5 v rms snr (note 1,2) a-weighted, @ fs = 48khz 98 db snr (note 1,2) a-weighted @ fs = 96khz 95 db snr (note 1,2) a-weighted @ fs = 192khz 92 db snr (note 1,2) a-weighted, @ fs = 48khz vdd = 3.3v 95 db snr (note 1,2) a-weighted @ fs = 96khz vdd = 3.3v 95 db snr (note 1,2) n on ?a? weighted @ fs = 48khz 92 db thd 1khz, 0dbfs -84 db dynamic range (note 2) 1khz, thd+n @ -60dbfs 90 98 db analogue output levels output level load = 10k ? , 0dbfs 1.2 v rms load = 10k ? , 0dbfs, (vdd = 3.3v) 0.79 v rms gain mismatch channel-to-channel 1 %fsr minimum resistance load to midrail or a.c. coupled 1 k ? to midrail or a.c. coupled (vdd = 3.3v) 1 k ? maximum capacitance load 5v or 3.3v 100 pf output d.c. level vdd/2 v power on reset (por) por threshold 2.4 v
wm8762 production data w pd, rev 4.6, november 2011 6 notes: 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input, measured ?a? we ighted over a 20hz to 20khz bandwidth. 2. all performance measurements done with 20khz low pass filter , and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. power down occurs 1.5 ? s after mclk stops. terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with n o signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the rm s values, of (noise + distortion)/signal. 4. stop band attenuation (db) - is the degree to which the frequency spectrum is attenuated (outside audio band). 5. channel separation (db) - also known as cross-talk. th is is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. power on reset (por) the wm8762 has an internal power-on-reset (por) circuit which is used to reset the digital logic into a default state after power up. a block diagr am of the reset circuit is shown in figure 1. figure 1 block diagram of power-on-reset the active low reset signal npor will be asserted low until vdd=2.4v, which means vmid rises to 1.2v. when this threshold has been reached, then the npor is released and the digital interface has been reset. this is illustrated in the diagram shown in figure 2.
wm8762 production data w pd, rev 4.6, november 2011 7 figure 2 generation of internal npor at power-on-reset figure 3 illustrates the npor generation when the power is removed. figure 3 generation of npor at power-off-reset
wm8762 production data w pd, rev 4.6, november 2011 8 master clock timing mclk t mclkl t mclkh t mclky figure 4 master clock timing requirements test conditions vdd = 5v, gnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information mclk master clock pulse width high t mclkh 8 ns mclk master clock pulse width low t mclkl 8 ns mclk master clock cycle time t mclky 20 ns mclk duty cycle 40:60 60:40 time from mclk stopping to power down. 1.5 12 ? s digital audio interface bckin lrcin t bch t bcl t bcy din t lrsu t ds t lrh t dh figure 5 digital audio data timing test conditions vdd = 5v, gnd = 0v, t a = +25 o c, fs = 48khz, mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bckin cycle time t bcy 40 ns bckin pulse width high t bch 16 ns bckin pulse width low t bcl 16 ns lrcin set-up time to bckin rising edge t lrsu 8 ns lrcin hold time from bckin rising edge t lrh 8 ns din set-up time to bckin rising edge t ds 8 ns din hold time from bckin rising edge t dh 8 ns
wm8762 production data w pd, rev 4.6, november 2011 9 device description general introduction the wm8762 is a high performance dac designed for digital consumer audio applications. the range of features make it ideally suited for use in dvd players, av receivers and other consumer audio equipment. the wm8762 is a complete 2-channel stereo audio digital-to-analogue converter, including digital interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo dac and output smoothing filters. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. a novel multi bit sigma-delta dac design is used, utilising a 128x oversampling rate to optimise signal to noise performance and offer increased clock jitter tolerance. (in ?high-rate? operation, the oversampling ratio is 64x for system clocks of 128fs or 192fs) operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between clock rates being automatically controlled. sample rates (fs) from less than 8khz to 192khz are allowed, provided the appropriate system clock is input. the audio data interface supports a 16-24-bit left justified interface format. a single 2.7-5.5v supply may be used, the output amplitude scaling with absolute supply level. low supply voltage operation and low current consumption combined with the low pin count small package make the wm8762 attractive for many consumer applications. the device is packaged in a small 8-pin soic. dac circuit description the wm8762 dac is designed to allow playback of 24-bit pcm audio or similar data with high resolution and low noise and distortion. sample rates up to 192khz may be used, with much lower sample rates acceptable provided that the ratio of sample rate (lrcin) to system master clock (mclk) is maintained at one of the required rates. the two dacs on the wm8762 are implemented using sigma-delta oversampled conversion techniques. these require that the pcm samples are digitally filtered and interpolated to generate a set of samples at a much higher rate than the input rate. this sample stream is then digitally modulated to generate a digital pulse stream that is then converted to analogue signals in a switched capacitor dac. the advantage of this technique is that the dac is linearised using noise shaping techniques, allowing the 24-bit resolution to be met using non-critical analogue components. a further advantage is that the high sample rate at the dac output means that smoothing filters on the output of the dac need only have fairly crude characteristics in order to remove the characteristic steps, or images, on the output of the dac. to ensure that generation of tones characteristic to sigma-delta converters is not a problem, dithering is used in the digital modulator and a higher order modulator is used. the multi-bit switched capacitor technique used in the dac reduces sensitivity to clock jitter, and dramatically reduces out of band noise compared to switched current or single bit techniques used in other implementations. the outputs of the 2 dacs are buffered out of the device by buffer amplifiers. these amplifiers will source load currents of several ma and sink current up to 1.5ma allowing significant loads to be driven. the output source is active and the sink is class a, i.e. fixed value, so greater loads might be driven if an external ?pull-down? resistor is connected at the output. typically an external low pass filter circuit will be used to remove residual out of band noise characteristic of delta sigma converters. however, the advanced multi-bit dac used in wm8762 produces far less out of band noise than single bit traditional sigma delta dacs, and so in many applications this filter may be removed, or replaced with a simple rc pole. dac output phase in the dac to analogue output, the analogue output data voutl/r, is a phase inverted representation of the digital input signal.
wm8762 production data w pd, rev 4.6, november 2011 10 clocking schemes in a typical digital audio system there is onl y one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. the external master clock can be applied directly through the mclk input pin with no configuration necessary for sample rate selection. note that on the wm8762, mclk is used to derive clocks for the dac path. the dac path consists of dac sampling clock, dac digital filter clock and dac digital audio interface timing. in a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the dac. the device can be powered down by stopping mc lk. in this state the power consumption is substantially reduced. digital audio interface wm8762 supports the left justified audio interface format. the wm8762 supports word lengths of 16-24 bits (msb first). the word length may be any value up to 24-bits. (if the word length shorter than 24-bits is used, the unused bits will be padded with zeros). in left justified mode, the msb of din is sampled by the wm8762 on the first rising edge of bckin following a lrcin transition. lrcin is high during the left samples and low during the right samples. figure 6 left justified mode timing diagram audio data sampling rates the master clock for wm8762 supports audio sampling rates from 128fs to 768fs, where fs is the audio sampling frequency (lrcin) typically 32khz, 44.1khz, 48khz, 96khz or 192khz. the master clock is used to operate the digital filters and the noise shaping circuits. the wm8762 has a master clock detection circuit that automatically determines the relation between the master clock frequency and the sampling rate (to within +/- 8 master clocks). if there is a greater than 8 clocks error, the interface shuts down the dac and mutes the output. the master clock should be synchronised with lrcin, although the wm8762 is tolerant of phase differences or jitter on this clock. sampling rate (lrcin) master clock frequency (mhz) (mclk) 128fs 192fs 256fs 384fs 512fs 768fs 32khz 4.096 6.144 8.192 12.288 16.384 24.576 44.1khz 5.6448 8.467 11.2896 16.9340 22.5792 33.8688 48khz 6.114 9.216 12.288 18.432 24.576 36.864 96khz 12.288 18.432 24.576 36.864 unavailable unavailable 192khz 24.576 36.864 unavailable unavail able unavailable unavailable table 1 master clock frequencies versus sampling rate if operating in 192fs or 384fs modes, the following conditions must be met, otherwise the wm8762 may behave in an unspecified manner: left channel right channel lrcin bckin din 1/fs n 3 2 1 n-2 n-1 lsb ms n 3 2 1 n-2 n-1 lsb ms
wm8762 production data w pd, rev 4.6, november 2011 11 1) after reset, ensure that lrclk and bclk are provided within 768 mclk periods of mclk starting up 2) if switching to 192fs or 384fs modes at any time during operation, reset the wm8762 by recycling the power digital filter characteristics parameter symbol test conditions min typ max unit passband edge -3db 0.487fs passband ripple f < 0.444fs ? 0.05 db stopband attenuation f > 0.555fs -60 db table 2 digital filter characteristics dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) figure 7 dac digital filter frequency response -44.1, 48 and 96khz -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 8 dac digital filter ripple -44.1, 48 and 96khz -80 -60 -40 -20 0 0 0.2 0.4 0.6 0.8 1 response (db) frequency (fs) figure 9 dac digital filter frequency response ? 192khz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 10 dac digital filter ripple ?192khz
wm8762 production data w pd, rev 4.6, november 2011 12 typical performance -120 -65 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 d b r b -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 11 wm8762 functionality thd+n vdd = 5v -120 -70 -117.5 -115 -112.5 -110 -107.5 -105 -102.5 -100 -97.5 -95 -92.5 -90 -87.5 -85 -82.5 -80 -77.5 -75 -72.5 d b r b -160 +0 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 dbfs figure 12 wm8762 functionality thd+n vdd = 3v
wm8762 production data w pd, rev 4.6, november 2011 13 applications information recommended external components figure 13 external component diagram recommended external components values component reference suggested value description c1 10 ? f de-coupling for vdd c2 0.1 ? f de-coupling for vdd c3 and c4 10 ? f output ac coupling caps to remove midrail dc level from outputs table 3 external components description
wm8762 production data w pd, rev 4.6, november 2011 14 recommended analogue low pass filter (optional) + _ + +vs -vs 10uf 51 ? 7.5k ? 680pf 1.8k ? 47k ? 4.7k ? 4.7k ? 1.0nf figure 14 recommended low pass filter (optional) an external low pass filter is recommended (see figure 20) if the device is driving a wideband amplifier. in some applications, a passive rc filter may be adequate. pcb layout recommendations care should be taken in the layout of the pcb that the wm8726 is to be mounted to. the following notes will help in this respect: 1. the vdd supply to the device should be as noise free as possible. this can be accomplished to a large degree with a 10uf bulk capacitor placed locally to the device and a 0.1uf high frequency decoupling capacitor placed as close to the vdd pin as possible. it is best to place the 0.1uf capacitor directly between the vdd and gnd pins of the device on the same layer to minimize track inductance and thus improve device decoupling effectiveness. 2. separate analogue and digital track routing from each other . the device is split into analogue (pins 5 ? 9) and digital (pins 1 ? 4 and pins 10 ? 14) sections that allow the routing of these signals to be easily separated. by physically separating analogue and digital signals, crosstalk from the pcb can be minimized. 3. use an unbroken solid gnd plane . to achieve best performance from the device, it is advisable to have either a gnd plane layer on a multilayer pcb or to dedicate one side of a 2 layer pcb to be a gnd plane. for double sided implementations it is best to route as many signals as possible on the device mounted side of the board, with the opposite side acting as a gnd plane. the use of a gnd pl ane greatly reduces any electrical emissions from the pcb and minimizes crosstalk between signals. an evaluation board is available for the wm8726 that demonstrates the above techniques and the excellent performance achievable from the dev ice. this can be ordered or the user manual downloaded from the wolfson web site at www.wolfsonmicro.com
wm8762 production data w pd, rev 4.6, november 2011 15 package drawing dm009.b d: 8 pin soic 3.9 mm symbols dimensions (mm) dimensions (inches) min max min max a 1.35 1.75 0.0532 0.0688 a 1 0.10 0.25 0.0040 0.0098 b 0.33 0.51 0.0130 0.0200 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 0.1890 0.1968 e 1.27 bsc 0.050 bsc e 3.80 4.00 0.1497 0.1574 h 0.25 0.50 0.0099 0.0196 h 5.80 6.20 0.2284 0.2440 l 0.40 1.27 0.0160 0.0500 0 o 8 o 0 o 8 o ref: jedec.95, ms-012 notes: a. all linear dimensions are in millimeters (inches). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm (0.010in). d. meets jedec.95 ms-012, variation = aa. refer to this specification for further details. c h x 45 o l a a1 seating plane -c- 0.10 (0.004) 4 1 d 5 8 e h b e
wm8762 production data w pd, rev 4.6, november 2011 16 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specificati ons in effect at the date of shipment. wolfson reserves the righ t to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. speci fic testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such sele ction or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectua l property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective thir d party owner. reproduction of information from wolfson datasheets is permissibl e only if reproduction is without alteration and is accompanie d by all associated copyright, proprietary and other notices (includi ng this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities acc epted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed the reon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
wm8762 production data w pd, rev 4.6, november 2011 17 revision history date rev originator changes 23/12/03 4.0 jmacd updated to production data order codes: leadfree and t&r options added, peak soldering temp added p3 29//09/04 4.1 jc pin configuration: pin 8 changed to voutr and pin 5 changed to voutl, p3 pin description: changes as above, p3 recommended external component diagram, changes as above, p12 25/07/06 4.2 jmacd order codes ? removed leaded codes, p3 important notice updated, p15 21/04/08 4.3 id added dac phase invertion comment ? p9 added por description and changed por threshold from 1.8v to 2.4v. to be consistent with other devices. removed ?wide body? from package information. 04/11/08 4.4 jmacd minimum temp updated from -25 to -40 o c, p2, p4 28/06/11 4.5 bt added 192fs and 384fs recommended operating conditions to avoid unspecified operation in audio data sampling rates section, p10 and p11. 26/09/11 4.6 jmacd order codes changed from wm8762ged/v and wm8762ged/rv to WM8762CGED and WM8762CGED/r to reflect change to copper wire bonding. 26/09/11 4.6 jmacd msl changed from msl2 to msl1.

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